This invention relates to a memory control system used in a computer system in which plural memories that are individually operable are connected with the same memory bus.
For shortening memory access time in a computer system provided with plural individually operable memories, it has been proposed to provide as many memory buses as there are the memories. In such case, as the number of memories increases the number of memory buses is also increased, and the number of data lines between the memories and the memory access source units also increases. However, in the case where the control units for the respective memories on the memory access source units are formed in a large scale integrated circuit, the number of the I/O lines for each unit is limited so that it is preferable to reduce the number of the data lines between the units. To this end, it has been proposed to connect the plural individually operable memories with the memory access source units through the same memory bus.
Where plural memories are connected with the same memory bus, execution of one memory access operation generally occupies the memory bus until this operation is terminated. Therefore, when the transfer of address information and data in a memory read operation is carried out with a pause therebetween using the same memory bus, the use of the memory bus in this memory read operation results in a free time between the termination of the address transfer and the initiation of the read data transfer, as shown in FIG. 7. Although the associated memory is in operation during this free time, some other memories connected with the memory bus can accept memory access. The prior art, for example JP-A-56-96311 does not provide for the memory bus during this free time.